In various electronic systems there arises a need for a circuit that provides an output a voltage which is a prescribed fraction of the voltage of an input source, for example one-half. This fraction should remain constant as the voltage of the input source varies for various reasons, including drift with temperature or aging.
Various circuits have been proposed for such use in the past. A simple form includes two pairs of Complementary Metal-Oxide-Silicon (CMOS) transistors connected so that the drain-source circuits of the four transistors are connected in series between opposite terminals of a power supply 15 to form a chain circuit 10 shown in FIG. 1. Circuit 10 includes P-channel Metal-Oxide-Silicon (MOS) transistor 11, N-channel MOS transistor 12, P-channel MOS transistor 13 and N-channel MOS transistor 14 serially connected in a chain or string which is connected to two terminals of power supply 15 (having an output voltage +V1) as shown. Moreover, each of the transistors is connected as a diode with its gate electrode shorted to its drain electrode so that it effectively acts as a resistor. In this arrangement, P-channel transistors 11 and 13 are matched to a one another in a one to one ratio, and N-channel transistors 12 and 14 are similarly matched to one another. As used throughout herein, the term matched, unless qualified, will indicate a one-to-one ratio of match. Because of the symmetry, the voltage at a central output terminal 16 between transistors 12 and 13 is one half (+V1/2) of the power supply voltage +V1 applied between the two ends of the transistor chain. In addition, the output voltage appearing at terminal 16 tracks changes in the voltage +V1 of the power supply 15.
One problem with this circuit is that because the four transistors are serially located between the terminals of the power supply 15, if the voltage +V1 of the power supply 15 is less than the sum of the four threshold voltages of the four transistors, the voltage at output terminal 16 is indeterminate because one or more of the transistors may not be biased on and thus the circuit 10 is effectively an open circuit.
To avoid this problem, various modifications of this basic circuit configuration have been proposed so as to reduce the sum of the threshold voltage drops between the two power supply terminals.
FIGS. 2 and 3 show two such variations which have been developed. Circuit 20, which is shown in FIG. 2, includes two pairs of complementary transistors 21, 22, 23 and 24 which are connected to have their drain-source circuits connected in series. The sources of transistors 21 and 24 connected to a separate one of the terminals of power supply 25 which has an output voltage +V2. In this instance, P-channel transistor 21 and N-channel transistor 24 are connected as diodes, while N-channel transistor 22 has its gate connected to one terminal of the power supply 25 and P-channel transistor 23 has its gate connected to the other terminal of the power supply 25. Again the two P-channel transistors are matched to one another, and the N-channel transistors are also matched to one another. The output voltage of circuit 20, which is approximately one half the voltage of power supply 25, is derived at a central output terminal 26 between transistors 22 and 23. In circuit 20 the threshold voltage drop between the two terminals to the voltage supply 25 is approximately only two threshold voltages. However, because of asymmetry resulting because the top half has P-channel transistor 21 connected as a diode while the bottom half has N-channel transistor 24 so connected, the gate-to-source bias voltages on the two CMOS pairs of transistors tends to be different. This limits the range of input voltages (the voltage +V2 of the power supply 25) over which the output voltage (which appears at terminal 26) tracks any drifts in +V2. Typically, close tracking is limited to about a 5% range.
A circuit 30, which is shown in FIG. 3, includes two pairs of complementary transistors 31, 32, 33, and 34 which are connected to have their drain-source circuits connected in series. The sources of transistors 31 and 34 are connected to a separate one of terminals of power supply 35. Power supply 35 has an output voltage +V3. N-channel transistor 32 and P-channel transistors 33 are connected as diodes while transistors 31 and 34 have their gates connected to opposite terminals of a power supply 35 having an output voltage +V3. Again, the output voltage derived at an output terminal 36 of circuit 30 tracks the power supply input voltage only over a limited range because of the asymmetry.